XC2S15-TQ144AMS

Product Summary

The XC2S15-TQ144AMS is a Spartan-II FPGA. The XC2S15-TQ144AMS has a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. These functional elements are interconnected by a powerful hierarchy of versatile routing channels. The XC2S15-TQ144AMS is customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes.

Parametrics

XC2S15-TQ144AMS absolute maximum ratings: (1)VCCINT Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF Input reference voltage: –0.5 to 3.6 V; (4)VIN Input voltage relative to GND 5V tolerant I/O: –0.5 to 5.5 V; (5)No 5V tolerance: –0.5 to VCCO+0.5 V; (6)VTS Voltage applied to 3-state output 5V tolerant I/O: –0.5 to 5.5 V; (7)No 5V tolerance: –0.5 to VCCO+0.5 V; (8)TSTG Storage temperature (ambient): –65 to +150 ℃; (9)TJ Junction temperature: +125 ℃.

Features

XC2S15-TQ144AMS features: (1)Fully PCI compliant; (2)Low-power segmented routing architecture; (3)Full readback ability for verification/observability; (4)Dedicated carry logic for high-speed arithmetic; (5)Dedicated multiplier support; (6)Cascade chain for wide-input functions; (7)Abundant registers/latches with enable, set, reset; (8)Four dedicated DLLs for advanced clock control; (9)Four primary low-skew global clock distribution nets; (10)IEEE 1149.1 compatible boundary scan logic; (11)Low cost packages available in all densities; (12)Family footprint compatibility in common packages; (13)16 high-performance interface standards; (14)Hot swap Compact PCI friendly; (15)Zero hold time simplifies system timing.

Diagrams