TSB81BA3DPFP

Product Summary

The TSB81BA3DPFP is a three-port cable transceiver/arbiter needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB81BA3DPFP is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. The TSB81BA3DPFP is powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1 μF and smaller decoupling capacitors, and the DVDD-CORE terminals separately decoupled with a 1 μF and smaller decoupling capacitors.

Parametrics

TSB81BA3DPFP absolute maximum ratings: (1)Supply voltage range, VDD: -0.3 V to 4 V; (2)Input voltage range, VI: -0.5 V to VDD + 0.5 V; (3)Output voltage range at any output, VO: -0.5 V to VDD + 0.5 V; (4)Continuous total power dissipation: See Dissipation Rating Table; (5)Operating free air temperature, TA: TSB81BA3D: 0℃ to 70℃; (6)Storage temperature range, Tstg: -65℃ to 150℃; (7)Lead temperature 1,6 mm (1/16 inch)from case for 10 seconds: 260℃.

Features

TSB81BA3DPFP features: (1)Fully Supports Provisions of IEEE P1394b Revision 1.33+ at 1-Gigabit Signaling Rates; (2)Fully Supports Provisions of IEEE 1394a-and 1394-1995 Standard for High Performance Serial Bus; (3)Fully Interoperable With Firewire i.LINK and SB1394, Implementation of IEEE Std 1394; (4)Provides Three Fully Backward Compatible, (1394a-2000 Fully Compliant)Bilingual P1394b Cable Ports at up to 800 Megabits per Second (Mbits/s); (5)Provides Three 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Mbits/s; (6)Data Interface to Link-Layer Controller Pin Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz)or 1394b Mode (8 Parallel Bits at 98.304 MHz); (7)Interface to Link-Layer Controller Supports Low Cost TI Bus-Holder Isolation; (8)Interoperable With Link-Layer Controllers Using 3.3-V Supplies; (9)Interoperable With Other 1394 Physical Layers (PHYs)Using 1.8-V, 3.3-V, and 5-V Supplies; (10)Low Jitter, External Crystal Oscillator Provides Transmit and Receive Data at 100/200/400/800 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz; (11)Separate Bias (TPBIAS)for Each Port; (12)Low Cost, High Performance 80-Pin TQFP (PFP)Thermally Enhanced Package.

Diagrams