SAA7111AH

Product Summary

The SAA7111AH is an Enhanced Video Input Processor (EVIP). The SAA7111AH is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M, NTSC-Japan NTSC N and SECAM), a brightness/contrast/saturation control circuit, a colour space matrix (see Fig.1) and a 27 MHz VBI-data bypass. The pure 3.3 V CMOS circuit SAA7111AH, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. TheSAA7111AH accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled. The SAA7111AH then supports several text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.

Parametrics

SAA7111AH absolute maximum ratings: (1)VDDD digital supply voltage: -0.5 to +4.6 V; (2)VDDA analog supply voltage: -0.5 to +4.6 V; (3)Vi(A)input voltage at analog inputs: -0.5 to VDDA + 0.5 (4.6 max.)V; (4)Vo(A)output voltage at analog output -0.5 to VDDA + 0.5 V; (5)Vi(D)input voltage at digital inputs and outputs outputs in 3-state: -0.5 to +5.5 V; (6)Vo(D)output voltage at digital outputs outputs active: -0.5 to VDDD + 0.5 V; (7)DVSS voltage difference between VSSAall and VSSall: 100 mV; (8)Tstg storage temperature: -65 to +150 ℃; (9)Tamb operating ambient temperature: 0 to 70 ℃; (10)Tamb(bias)operating ambient temperature under bias: -10 to +80 ℃; (11)Vesd electrostatic discharge all pins: -2000 to +2000 V.

Features

SAA7111AH features: (1)Two analog preprocessing channels; (2)Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel; (3)Switchable white peak control; (4)Two built-in analog anti-aliasing filters; (5)Two 8-bit video CMOS analog-to-digital converters; (6)On-chip clock generator; (7)Line-locked system clock frequencies; (8)Digital PLL for horizontal-sync processing and clock generation; (9)Requires only one crystal (24.576 MHz)for all standards; (10)Horizontal and vertical sync detection; (11)Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards; (12)Odd/even field identification by a non interlace CVBS input signal; (13)Fix level for RGB output format during horizontal blanking; (14)720 active samples per line on the YUV bus; (15)One user programmable general purpose switch on an output pin; (16)Built-in line-21 text slicer; (17)A 27 MHz Vertical Blanking Interval (VBI)data bypass programmable by I2C-bus for INTERCAST applications; (18)Power-on control; (19)Two via I2C-bus switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0)and AD2 (7 to 0); (20)Chip enable function (reset for the clock generator and power save mode up from chip version 3); (21)Compatible with memory-based features (line-locked; (22)clock).

Diagrams